NDLI: The Associative Linear Array Processor

Content Provider	IEEE Xplore Digital Library
Author	Finnila, Charles A. Love, Hubert H.
Copyright Year	1968
Abstract	The associative linear array processor (ALAP) is a new approach to making large associative processors practical. Data storage in shift registers, bit-serial arithmetic, LSI word cells comprehensive arithmetic capability within the memory array, and electronic fault isolation are all utilized. The processor is a linear array of word cells, each containing memory and arithmetic logic. All connections to the word cells are by means of common buses except for the multiuse chaining channel. As with most operations within word cells, the current function of the chaining channel in each word is controlled by the combination of common control lines and the states of flag flip-flops in each word. This allows different chaining channel action in different words. Among its many uses the chaining channel can be used to resolve conflicts of multiple associative memory matches, to perform interword arithmetic, or to sort data as they are being input to the associative memory. In the ALAP project effort conducted at Hughes, wafers containing arrays of ALAP cells have been fabricated using LSI technology. A complete hardware/software system using the ALAP has been fabricated and checked out, along with two application programs of nontrivial magnitude.
Sponsorship	IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page	112
Ending Page	125
Page Count	14
File Size	4279253
File Format	PDF
ISSN	00189340
Volume Number	C-26
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1977-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Relays Clocks Arrays Shift registers Large scale integration Associative memory Data mining parallel processing associative processor system cellular logic array data retrieval electronic fault isolation fault-tolerant logic highly parallel arithmetic large-scale integration (LSI)
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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