NDLI: The charge-coupled RAM cell concept

Content Provider	IEEE Xplore Digital Library
Author	Tasch, A.F. Frye, R.C.
Copyright Year	1966
Description	A new concept in MOS dynamic RAM cells is described and demonstrated. The charge-coupled RAM (CC RAM) cell combines the storage capacity and transfer gate of the one-transistor cell into a single gate. The resulting cell is simpler than the conventional one-transistor cell and possesses significant advantages in packing density and potentially higher yield. One of the variations of the CC RAM cell concept results in a cell whose operation is identical (voltage and timing) to that of the present one-transistor cell. In addition, the CC RAM cell fabrication is essentially the same as the present one-transistor cell process. The CC RAM is an attractive candidate for the next generation RAM's.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	58
Ending Page	63
Page Count	6
File Size	1097739
File Format	PDF
ISSN	00189200
Volume Number	11
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1976-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Read-write memory Charge coupled devices Random access memory Production Fabrication Ion beams Microwave devices Physics Aircraft DRAM chips
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

VMOS memory technology

A 64Kx1 bit dynamic ED-MOS RAM

An n-Well CMOS Dynamic RAM

dRAM Design Using the Taper-Isolated Dynamic RAM Cell

A 256K dynamic RAM with page-nibble mode

The BO-MOS RAM cell

A low-power sub 100 ns 256K bit dynamic RAM

A 16 DIP, 64 kbit, static MOS-RAM

The twin-port memory cell

The charge-coupled RAM cell concept

Similar Documents

VMOS memory technology

A 64Kx1 bit dynamic ED-MOS RAM

An n-Well CMOS Dynamic RAM

dRAM Design Using the Taper-Isolated Dynamic RAM Cell

A 256K dynamic RAM with page-nibble mode

The BO-MOS RAM cell

A low-power sub 100 ns 256K bit dynamic RAM

A 16 DIP, 64 kbit, static MOS-RAM

The twin-port memory cell

The charge-coupled RAM cell concept