NDLI: Diagnosis and Fault Equivalence in Combinational Circuits

Content Provider	IEEE Xplore Digital Library
Author	Roy, B.K.
Copyright Year	1968
Abstract	Two procedures are presented: one for diagnosis of single-gate failures and the other for deriving equivalence classes of single faults. Both procedures require use of a diagnostic table which lists gate sensitivities and primary output values for all input patterns in a set of tests which contains at most U tests, where U is an upper bound derived in the text. A gate is defined to be an n-input single-output combinational circuit (n ≥ 1) and a failure is any detectable transformation of the correct gate function. The information contained in a diagnostic table can be used to locate a faulty gate and describe its failed function. Equivalence classes are derived from a diagnostic table by first specifying the primary output values in accordance with a theorem given in the text and then deriving the corresponding gate functions. Examples are given to illustrate both the procedures.
Sponsorship	IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page	955
Ending Page	963
Page Count	9
File Size	2862807
File Format	PDF
ISSN	00189340
Volume Number	C-23
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1974-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Combinational circuits, equivalence classes, fault diagnosis, fault testing, single-gate failures.
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Diagnosis of Single-Gate Failures in Combinational circuits

Fault Equivalence in Combinational Logic Networks

R70-12 Diagnosis of Single-Gate Failures in Combinational Circuits

Fault Testing and Diagnosis in Combinational Digital Circuits

Recursion and Testing of Combinational Circuits

A Simple Random Test Procedure for Detection of Single Intermittent Fault in Combinational Circuits

Transition Count Testing of Combinational Logic Circuits

Minimal Fault Tests for Redundant Combinational Networks

Fault Detection in Fanout-Free Combinational Networks

Diagnosis and Fault Equivalence in Combinational Circuits

Similar Documents

Diagnosis of Single-Gate Failures in Combinational circuits

Fault Equivalence in Combinational Logic Networks

R70-12 Diagnosis of Single-Gate Failures in Combinational Circuits

Fault Testing and Diagnosis in Combinational Digital Circuits

Recursion and Testing of Combinational Circuits

A Simple Random Test Procedure for Detection of Single Intermittent Fault in Combinational Circuits

Transition Count Testing of Combinational Logic Circuits

Minimal Fault Tests for Redundant Combinational Networks

Fault Detection in Fanout-Free Combinational Networks

Diagnosis and Fault Equivalence in Combinational Circuits