NDLI: Performance Analysis of MPSK Phase Detectors for Carrier Synchronization PLLs at Low SNRs

Content Provider	IEEE Xplore Digital Library
Author	Wei Jiang Yifei Cui
Copyright Year	1997
Abstract	In this letter, we analyze the performance of a category of phase detectors (PDs) for carrier synchronization phase-locked loops (PLLs) in M-ary phase shift keying (MPSK) receivers working at low signal-to-noise ratios (SNRs). These PDs have the property that their outputs are functions of the inputs' phase only, and thus, their performance is independent of the automatic gain control (AGC) circuits. We deduce closed-form expressions about the linearized gain and equivalent noise variance of these PDs when SNR goes to zero and sum up simple approximate formulas for three typical PDs at all SNRs. We also prove that the modified Mth-power PD performs asymptotically best in this category of PDs as SNR goes to zero.
Starting Page	2133
Ending Page	2136
Page Count	4
File Size	156344
File Format	PDF
ISSN	10897798
Volume Number	18
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Signal to noise ratio Detectors Performance evaluation Synchronization Approximation methods PLL carrier synchronization equivalent noise variance low SNR linearized gain MPSK phase detector Carrier synchronization
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Modeling and Simulation Computer Science Applications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Robust M-PSK phase detectors for carrier synchronization PLLs in coherent receivers: theory and simulations

(Phase Lock Loops): the carrier synchronization PLL

A Robust NDA Carrier Tracking Method for LDPC-Coded Systems With Symbol Rate Sampling

Design of low update rate phase locked loops with application to carrier tracking in OFDM systems

One computer-aided equivalent circuit model of a MEMS phase detector applied in phase locked loops

Decision directed versus non-data aided plls: A comparative review

DESIGN OF DIGITAL PLL USING OPTIMIZED PHASE NOISE VCO

A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference

PLL performance : simulation and design

Performance Analysis of MPSK Phase Detectors for Carrier Synchronization PLLs at Low SNRs

Similar Documents

Robust M-PSK phase detectors for carrier synchronization PLLs in coherent receivers: theory and simulations

(Phase Lock Loops): the carrier synchronization PLL

A Robust NDA Carrier Tracking Method for LDPC-Coded Systems With Symbol Rate Sampling

Design of low update rate phase locked loops with application to carrier tracking in OFDM systems

One computer-aided equivalent circuit model of a MEMS phase detector applied in phase locked loops

Decision directed versus non-data aided plls: A comparative review

DESIGN OF DIGITAL PLL USING OPTIMIZED PHASE NOISE VCO

A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference

PLL performance : simulation and design

Performance Analysis of MPSK Phase Detectors for Carrier Synchronization PLLs at Low SNRs