NDLI: A Cascode Feedback Bias Technique for Linear CMOS Power Amplifiers in a Multistage Cascode Topology

Content Provider	IEEE Xplore Digital Library
Author	Hamhee Jeon Kun-Seok Lee Ockgoo Lee Kyu Hwan An Youngchang Yoon Hyungwook Kim Kobayashi, K.W. Chang-Ho Lee Kenney, J.S.
Copyright Year	1963
Abstract	A novel feedback bias technique for a multistage cascode topology is developed to improve the linearity and reliability of power amplifiers (PAs). Due to the large parasitic capacitance and low substrate resistivity of CMOS technology, signal swings are coupled between the ports of transistors. The proposed method utilized the RF leakage signals at the gate of common-gate (CG) transistor in a cascode topology for employing negative feedback, which not only enhances the linearity of the PA, but also alleviates the voltage stress between the gate and the drain of the CG device in a cascode topology from 4.5 to 1.9 V. This technique requires no additional components or space and is easily applicable to the multistage cascode topology, which is one of the most popular structures of CMOS PA designs. In order to prove the concept, a 1.95-GHz fully integrated linear PA was implemented in a 0.18- μm CMOS technology. With a 3.4-V power supply, the PA transmits a saturated output power of 26 dBm with a power-added efficiency (PAE) of 46.4%, and a linear output power of 23.5 dBm with a PAE of 40% using a 3 GPP WCDMA modulated signal. The PA occupies 1.60 × 0.52 mm². This PA demonstrates the potential of the highly efficient CMOS PA design approach for wireless communication standards.
Sponsorship	IEEE Microwave Theory and Techniques Society
Starting Page	890
Ending Page	901
Page Count	12
File Size	3087330
File Format	PDF
ISSN	00189480
Volume Number	61
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transistors Logic gates CMOS integrated circuits Topology Negative feedback CMOS technology Reliability WCDMA AM–PM bias cascode CMOS efficiency feedback linearity power amplifier (PA) reliability
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electrical and Electronic Engineering Radiation

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Integrated Bias Circuits of RF CMOS Cascode Power Amplifier for Linearity Enhancement

A Feedback Technique to Compensate for AM-PM Distortion in Linear CMOS Class-F Power Amplifier

CMOS Saturated Power Amplifier With Dynamic Auxiliary Circuits for Optimized Envelope Tracking

Linearization of CMOS Cascode Power Amplifiers Through Adaptive Bias Control

A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a $+$ 27.1 dBm WCDMA CMOS Power Amplifier

A WLAN RF CMOS PA With Large-Signal MGTR Method

A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion

A Charging Acceleration Technique for Highly Efficient Cascode Class-E CMOS Power Amplifiers

Design of CMOS Power Amplifiers

A Cascode Feedback Bias Technique for Linear CMOS Power Amplifiers in a Multistage Cascode Topology

Similar Documents

Integrated Bias Circuits of RF CMOS Cascode Power Amplifier for Linearity Enhancement

A Feedback Technique to Compensate for AM-PM Distortion in Linear CMOS Class-F Power Amplifier

CMOS Saturated Power Amplifier With Dynamic Auxiliary Circuits for Optimized Envelope Tracking

Linearization of CMOS Cascode Power Amplifiers Through Adaptive Bias Control

A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a $+$ 27.1 dBm WCDMA CMOS Power Amplifier

A WLAN RF CMOS PA With Large-Signal MGTR Method

A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion

A Charging Acceleration Technique for Highly Efficient Cascode Class-E CMOS Power Amplifiers

Design of CMOS Power Amplifiers

A Cascode Feedback Bias Technique for Linear CMOS Power Amplifiers in a Multistage Cascode Topology