NDLI: Design and Analysis of Digital-Assisted Bandwidth-Enhanced Miller Divider in <formula formulatype=inline> <tex Notation=TeX>$ {hbox {0.18-}}mu{hbox {m}}$</tex></formula> CMOS Process

Content Provider	IEEE Xplore Digital Library
Author	Yen-Hung Kuo Jeng-Han Tsai Tian-Wei Huang Huei Wang
Copyright Year	1963
Abstract	A bandwidth-enhanced technique for a Miller divider is presented in this paper. The proposed frequency divider consists of a band-switched Miller divider and digital-assisted circuit to switch the resonator automatically. The proposed frequency divider is implemented in 0.18-μm CMOS technology and has a measured 57.4% bandwidth from 8.2 to 14.8 GHz at an input power of 0 dBm. The dc consumption is 12 mW. Compared to the previously reported Miller dividers, the proposed circuit achieves the widest fractional bandwidth.
Sponsorship	IEEE Microwave Theory and Techniques Society
Starting Page	3769
Ending Page	3777
Page Count	9
File Size	2431536
File Format	PDF
ISSN	00189480
Volume Number	60
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Detectors Frequency conversion Calibration Bandwidth Impedance Resonant frequency Switches regenerative frequency divider CMOS digital-assisted circuit Miller divider
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electrical and Electronic Engineering Radiation

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Design and Analysis of Digital-Assisted Bandwidth-Enhanced Miller Divider in $ {hbox {0.18-}}mu{hbox {m}}$ CMOS Process