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Multiple embedded processors for fault-tolerant computing
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Katanyoutanant, Sunant Burke, Gary Bolotin, Gary Watson, Robert Wang, Mandy |
| Copyright Year | 2005 |
| Description | A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them. |
| File Size | 89630 |
| Page Count | 1 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_20110016476 |
| Archival Resource Key | ark:/13960/t8md3wm34 |
| Language | English |
| Publisher Date | 2005-12-01 |
| Access Restriction | Open |
| Subject Keyword | Man/system Technology And Life Support Fault Tolerance Single Event Upsets Prototypes Embedded Computer Systems Central Processing Units Architecture Computers Field-programmable Gate Arrays Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Technical Report |
