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Method for characterizing the upset response of cmos circuits using alpha-particle sensitive test circuits
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Copyright Year | 1995 |
| Description | A method for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. A technique utilizing test structures to quickly and inexpensively characterize the SEU sensitivity of standard cell latches intended for use in a space environment. This bench-level approach utilizes alpha particles to induce upsets in a low LET sensitive 4-k bit test SRAM. This SRAM consists of cells that employ an offset voltage to adjust their upset sensitivity and an enlarged sensitive drain junction to enhance the cell's upset rate. |
| File Size | 998359 |
| Page Count | 19 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_20080007429 |
| Archival Resource Key | ark:/13960/t7sn54436 |
| Language | English |
| Publisher Date | 1995-03-07 |
| Access Restriction | Open |
| Subject Keyword | Electronics And Electrical Engineering Integrated Circuits Patents Particle Interactions Cmos Single Event Upsets Alpha Particles Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Patent |
