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Synchronous clock stopper for microprocessor
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Copyright Year | 1985 |
| Description | A synchronous clock stopper circuit for inhibiting clock pulses to a microprocessor in response to a stop request signal, and for reinstating the clock pulses in response to a start request signal thereby to conserve power consumption of the microprocessor when used in an environment of limited power. The stopping and starting of the microprocessor is synchronized, by a phase tracker, with the occurrences of a predetermined phase in the instruction cycle of the microprocessor in which the I/O data and address lines of the microprocessor are of high impedance so that a shared memory connected to the I/O lines may be accessed by other peripheral devices. The starting and stopping occur when the microprocessor initiates and completes, respectively, an instruction, as well as before and after transferring data with a memory. Also, the phase tracker transmits phase information signals over a bus to other peripheral devices which signals identify the current operational phase of the microprocessor. |
| File Size | 455638 |
| Page Count | 6 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_20080005900 |
| Archival Resource Key | ark:/13960/t2h75995g |
| Language | English |
| Publisher Date | 1985-10-01 |
| Access Restriction | Open |
| Subject Keyword | Electronics And Electrical Engineering Patents Microprocessors Circuits Clocks Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Patent |
