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Chip connectivity verification program
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Copyright Year | 1999 |
| Description | A method for testing electrical connectivity between conductive structures on a chip that is preferably layered with conductive and nonconductive layers. The method includes determining the layer on which each structure is located and defining the perimeter of each structure. Conductive layer connections between each of the layers are determined, and, for each structure, the points of intersection between the perimeter of that structure and the perimeter of each other structure on the chip are also determined. Finally, electrical connections between the structures are determined using the points of intersection and the conductive layer connections. |
| File Size | 1266131 |
| Page Count | 20 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_20080004490 |
| Archival Resource Key | ark:/13960/t00052w9h |
| Language | English |
| Publisher Date | 1999-09-07 |
| Access Restriction | Open |
| Subject Keyword | Computer Operations And Hardware Electrical Resistivity Patents Chips Memory Devices Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Patent |
