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Design of a massively parallel computer using bit serial processing elements
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Piatt, Jason E. Zheng, Jianqing Aburdene, Maurice F. Khouri, Kamal S. |
| Copyright Year | 1995 |
| Description | A 1-bit serial processor designed for a parallel computer architecture is described. This processor is used to develop a massively parallel computational engine, with a single instruction-multiple data (SIMD) architecture. The computer is simulated and tested to verify its operation and to measure its performance for further development. |
| File Size | 580921 |
| Page Count | 24 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19950015989 |
| Archival Resource Key | ark:/13960/t09w5ch6m |
| Language | English |
| Publisher Date | 1995-01-24 |
| Access Restriction | Open |
| Subject Keyword | Gates Circuits Performance Tests Computerized Simulation Architecture Computers Design Analysis Memory Computers Parallel Processing Computers Logic Circuits Simd Computers Interprocessor Communication Massively Parallel Processors Bits Time Sharing Communication Networks Ntrs Nasa Technical Reports ServerĀ (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Technical Report |