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Hardware proofs using ehdm and the rsre verification methodology
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Butler, Ricky W. Sjogren, Jon A. |
| Copyright Year | 1988 |
| Description | Examined is a methodology for hardware verification developed by Royal Signals and Radar Establishment (RSRE) in the context of the SRI International's Enhanced Hierarchical Design Methodology (EHDM) specification/verification system. The methodology utilizes a four-level specification hierarchy with the following levels: functional level, finite automata model, block model, and circuit level. The properties of a level are proved as theorems in the level below it. This methodology is applied to a 6-bit counter problem and is critically examined. The specifications are written in EHDM's specification language, Extended Special, and the proofs are improving both the RSRE methodology and the EHDM system. |
| File Size | 3007816 |
| Page Count | 94 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19890004631 |
| Archival Resource Key | ark:/13960/t0tr0sx89 |
| Language | English |
| Publisher Date | 1988-12-01 |
| Access Restriction | Open |
| Subject Keyword | Hierarchies Specifications Methodology Proving Computer Systems Design Hardware High Level Languages Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Technical Report |
