Extended Lock Range Zero-Crossing Digital Phase-Locked Loop with Time Delay

Content Provider	Directory of Open Access Journals (DOAJ)
Author	Nasir Qassim
Abstract	The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop. A solution that has been previously suggested is the introduction of a time delay in the feedback path of the loop to allow the digital circuits to complete their sample processing before the next sample is received. However, this added delay will limit the stable operation range and hence lock range of the loop. The objective of this work is to extend the lock range of ZCDPLL with time delay by using a chaos control. The tendency of the loop to diverge is measured and fed back as a form of linear stabilization. The lock range extension has been confirmed through the use of a bifurcation diagram, and Lyapunov exponent.
Related Links	http://dx.doi.org/10.1155/WCN.2005.413
ISSN	16871472
e-ISSN	16871499
Journal	EURASIP Journal on Wireless Communications and Networking
Issue Number	3
Volume Number	2005
Language	English
Publisher	SpringerOpen
Publisher Date	2005-01-01
Publisher Place	United Kingdom
Access Restriction	Open
Subject Keyword	Telecommunication Electronics Nonuniform Sampling Digital Phase Locked Loops Chaos Control
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications Computer Science Applications