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On-chip inductance modeling and rlc extraction of vlsi interconnects for circuit simulation (2000)
| Content Provider | CiteSeerX |
|---|---|
| Author | Qi, Xiaoning Young, Tak Wang, Gaofeng Yu, Zhiping Dutton, Robert W. |
| Description | in Proceedings of the IEEE Custom Integrated Circuits Conference |
| Abstract | Abstract- On-Chip inductance modeling of VLSI intercon-nects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise. I. |
| File Format | |
| Publisher Date | 2000-01-01 |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Proceeding Conference Proceedings |
