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Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing £
| Content Provider | CiteSeerX |
|---|---|
| Author | Lin, Jai-Ming Pan, Song-Ra Chang, Yao-Wen |
| Abstract | Architecture and CAD are closely related issues in FPGA design. Routing architecture design shall optimize routability and facilitate router development; on the other hand, router design shall consider the specific properties of routing architectures to optimize the performance of the router. In this paper, we propose effective and efficient unified matching-based algorithms for array-based FPGA routing and segmentation design. For the segmentation design, we consider the similarity of input routing instances and formulate a net-matching problem to construct the optimal segmentation architecture. For the router design, we present a matching-based timing-driven routing algorithm which can consider a versatile set of routing segments. Experimental results show that our designed segmentations significantly outperform those used in commercially available FPGAs. For example, our designed segmentations achieve, on average, 14.6 % and 19.7 % improvements in routability, compared with those used in the Lucent Technologies ORCA 2C-series and the Xilinx XC4000E-series FPGAs, respectively. 1 |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Array-based Fpga Segmentation Design Graph Matching-based Algorithm Segmentation Design Router Design Versatile Set Facilitate Router Development Array-based Fpga Routing Specific Property Available Fpgas Optimal Segmentation Architecture Matching-based Timing-driven Routing Algorithm Efficient Unified Matching-based Algorithm Related Issue Xilinx Xc4000e-series Fpgas Net-matching Problem Fpga Design Architecture Design Lucent Technology Orca 2c-series |
| Content Type | Text |
