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False-Noise Analysis using Logic Implications (2001)
| Content Provider | CiteSeerX |
|---|---|
| Author | Glebov, Alexey Gavrilov, Sergey Blaauw, David Sirichotiyakul, Supamas Oh, Chanhee Zolotov, Vladimir |
| Description | Cross-coupled noise analysis has become a critical concern in today’s VLSI designs. Typically, noise analysis makes an assumption that all aggressing nets can simultaneously switch in the same direction. This creates a worst-case noise pulse on the victim net that often leads to false noise violations. In this paper, we present a new approach that uses logic implications to identify the maximum set of aggressor nets that can inject noise simultaneously under the logic constraints of the circuit. We propose an approach to efficiently generate logic implications from a transistor-level description and propagate them in the circuit using ROBDD representations and a newly proposed laterial propagation method. We then show that the problem of finding the worst case logically feasible noise can be represented as a maximum weighted independent set problem and show how to efficiently solve it. Initially, we restrict our discussion to zero-delay implications, which are valid for glitch-free circuits and then extend our approach to timed implications. The proposed approaches were implemented in an industrial noise analysis tool and results are shown for a number of industrial test cases. We demonstrate that a significant reduction in the number of noise failures can be obtained from considering the logic implications as proposed in this paper, underscoring the need for false-noise analysis. 2 in Proc. ICCAD |
| File Format | |
| Language | English |
| Publisher Date | 2001-01-01 |
| Access Restriction | Open |
| Subject Keyword | Industrial Test Case False-noise Analysis Transistor-level Description Significant Reduction Robdd Representation Cross-coupled Noise Analysis Industrial Noise Analysis Tool Zero-delay Implication Critical Concern Logic Implication Noise Failure Feasible Noise Noise Violation Glitch-free Circuit New Approach Victim Net Timed Implication Laterial Propagation Method Maximum Set Noise Analysis Worst-case Noise Pulse Vlsi Design Logic Constraint Aggressor Net |
| Content Type | Text |
| Resource Type | Article |
