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Improving Nanoelectronic Designs Using a Statistical Approach to Identify Key Parameters in Circuit Level SEU Simulations
| Content Provider | CiteSeerX |
|---|---|
| Author | Ness, Drew C. Hescott, Christian J. Lilja, David J. |
| Abstract | Abstract — One of the key challenges in nanoelectronics design is the decreasing reliability due to radiation induced single-event upsets. Without detailed device level simulations or physical experimentation, circuit level models can generate misleading reliability information. We present the results from a screening experiment to identify significant parameters in circuit level SEU simulations. We show that cell supply voltage, sizing parameters, and transient waveform descriptions have an important impact on design and should therefore be considered with care in circuit level designs. Larger variations in parameters can lead to soft error rate estimates that vary by more than 4 orders of magnitude, even small variations can lead to 15x variation in soft error rate estimation for a design. We present our methodology for screening and a ranking based on significance of several parameters involved in soft error simulation at the SPICE level. Index Terms — circuit level reliability, single event upset (SEU), soft-error rate (SER), Plackett and Burman design, Qcrit I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Circuit Level Seu Simulation Nanoelectronic Design Statistical Approach Identify Key Parameter Significant Parameter Single Event Upset Soft Error Rate Estimate Small Variation Induced Single-event Upset Soft Error Simulation Important Impact Index Term Transient Waveform Description Physical Experimentation Burman Design Soft Error Rate Estimation Key Challenge Spice Level Level Reliability Supply Voltage Detailed Device Level Simulation Soft-error Rate Circuit Level Design Several Parameter Circuit Level Model Nanoelectronics Design Larger Variation Misleading Reliability Information |
| Content Type | Text |