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Bit-level partial evaluation of synchronous circuits. In preparation, draft available at http://findatlantis.com/mypapers (2004)
| Content Provider | CiteSeerX |
|---|---|
| Author | Thompson, Sarah |
| Abstract | Partial evaluation has been known for some time to be very effective when applied to software; in this paper we demonstrate that it can also be usefully applied to hardware. We present a bit-level algorithm that supports the partial evaluation of synchronous digital circuits. Full PE of combinational logic is noted to be equivalent to Boolean minimisation. A loop unrolling technique, supporting both partial and full unrolling, is described. Experimental results are given, showing that partial evaluation of a simple microprocessor against a ROM image is equivalent to compiling the ROM program directly into low level hardware. 1. |
| File Format | |
| Publisher Date | 2004-01-01 |
| Access Restriction | Open |
| Subject Keyword | Rom Image Com Mypapers Low Level Hardware Combinational Logic Full Unrolling Bit-level Algorithm Bit-level Partial Evaluation Partial Evaluation Loop Unrolling Technique Simple Microprocessor Synchronous Circuit Full Pe Experimental Result Boolean Minimisation Rom Program Synchronous Digital Circuit |
| Content Type | Text |
| Resource Type | Article |
