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Test Cost Reduction for SOCs Using Virtual TAMs and Lagrange Multipliers (2003)
| Content Provider | CiteSeerX |
|---|---|
| Author | Krasniewski, Mark D. Sehgal, Anuja Chakrabarty, Krishnendu Iyengar, Vikram |
| Abstract | Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically run at lower frequencies (10-50 MHz). The use of high-speed ATE channels to drive slower scan chains leads to an underutilization of resources, thereby resulting in an increase in testing time. We present a new technique to reduce the testing time and test cost by matching highspeed ATE channels to slower scan chains using the concept of virtual test access mechanisms (TAMs). We also present a new TAM optimization framework based on Lagrange multipliers. Experimental results are presented for three industrial circuits from the ITC’02 SOC test benchmarks. |
| File Format | |
| Publisher Date | 2003-01-01 |
| Access Restriction | Open |
| Subject Keyword | Lagrange Multiplier Testing Time 10-50 Mhz Automatic Test Equipment Soc Test Benchmark Abstract Test Cost Reduction Virtual Test Access Mechanism Highspeed Ate Channel Test Cost High-speed Ate Channel Experimental Result New Technique Tester Technology Industrial Circuit Scan Chain New Tam Optimization Framework Socs Using Virtual Tam |
| Content Type | Text |
| Resource Type | Proceeding |
