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ACompactandEfficientFPGA Implementation of the DES Algorithm
| Content Provider | CiteSeerX |
|---|---|
| Author | Díaz-Pérez, Arturo Rodríguez-Henriquez, Francisco Saqib, Nazar A. |
| Abstract | Abstract. In this paper we present an efficient and compact reconfigurable hardware implementation of the Data Encryption Standard (DES) algorithm. Our design was implemented on a VirtexE XCV400e device. As a strategy to reduce the associated design critical path, we utilized a parallel structure that allowed us to compute all the eight DES S-boxes simultaneously. Our DES round design achieved a data encryption/decryption rate of 274 Mbits/s occupying only 117 CLB slices. These results are quite competitive when compared with other reported reconfigurable hardware implementations of DES. Key Words: DES,FPGA,Parallelstructure. 1 |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | De S-boxes Clb Slice De Round Design Data Encryption Standard Data Encryption Decryption Rate Virtexe Xcv400e Device Associated Design Critical Path Parallel Structure De Algorithm Acompactandefficientfpga Implementation Reconfigurable Hardware Implementation Compact Reconfigurable Hardware Implementation |
| Content Type | Text |
| Resource Type | Article |
