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Processor-memory co-exploration using an architecture description language
| Content Provider | CiteSeerX |
|---|---|
| Author | Mishra, Prabhat Mamidipaka, Mahesh Dutt, Nikil |
| Abstract | Memory represents a major bottleneck in modern embedded systems in terms of cost, power, and performance. Traditionally, memory organizations for programmable embedded systems assume a fixed cache hierarchy. With the widening processor–memory gap, more aggressive memory technologies and organizations have appeared, allowing customization of a heterogeneous memory architecture tuned for specific target applications. However, such a processor–memory coexploration approach critically needs the ability to explicitly capture heterogeneous memory architectures. We present in this paper a language-based approach to explicitly capture the memory subsystem configuration, generate a memory-aware software toolkit, and perform coexploration of the processor–memory architectures. We present a set of experiments using our memory-aware architectural description language (ADL) to drive the exploration of the memory subsystem for the TI C6211 processor architecture, demonstrating cost, performance, and energy trade-offs. |
| File Format | |
| Volume Number | 3 |
| Journal | ACM Transactions on Embedded Computing Systems (TECS |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Processor-memory Co-exploration Architecture Description Language Heterogeneous Memory Architecture Energy Trade-off Processor Memory Coexploration Approach Language-based Approach Memory Subsystem Processor Memory Architecture Widening Processor Memory Gap Fixed Cache Hierarchy Memory Subsystem Configuration Memory-aware Software Toolkit Major Bottleneck Aggressive Memory Technology Programmable Embedded System Memory Organization Memory-aware Architectural Description Language Specific Target Application Ti C6211 Processor Architecture |
| Content Type | Text |
| Resource Type | Article |
