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A Parallel Genetic Algorithm for Performance-Driven VLSI Routing
| Content Provider | CiteSeerX |
|---|---|
| Abstract | Abstract — This paper presents a novel approach to solve the VLSI (very large scale integration) channel and switchbox routing problems. The approach is based on a parallel genetic algorithm (PGA) that runs on a distributed network of workstations. The algorithm optimizes both physical constraints (length of nets, number of vias) and crosstalk (delay due to coupled capacitance). The parallel approach is shown to consistently perform better than a sequential genetic algorithm when applied to these routing problems. An extensive investigation of the parameters of the algorithm yields routing results that are qualitatively better or as good as the best published results. In addition, the algorithm is able to significantly reduce the occurrence of crosstalk. Index Terms — Channel routing, crosstalk, parallel computation, parallel genetic algorithm, punctuated equilibria, switchbox routing, VLSI physical design. I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Parallel Genetic Algorithm Performance-driven Vlsi Routing Distributed Network Algorithm Yield Switchbox Routing Problem Parallel Computation Physical Constraint Sequential Genetic Algorithm Extensive Investigation Vlsi Physical Design Parallel Approach Index Term Channel Routing Switchbox Routing Large Scale Integration |
| Content Type | Text |
| Resource Type | Article |
