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Utilizing don’t care states in SAT-based bounded sequential problems (2005)
| Content Provider | CiteSeerX |
|---|---|
| Author | Safarpour, Sean Veneris, Andreas |
| Description | in Great Lakes Symp. VLSI, 2005 |
| Abstract | Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequential equivalence checking rely on fast and robust SAT solvers. In this work, we introduce a technique that improves the performance of the underlying SAT solver for bounded sequential problems by taking advantage of a design’s don’t care states. We develop cost effective methods of filtering, replicating and applying the don’t care states to the original problem thus reducing the search space. Experiments demonstrate the effectiveness of the proposed method on ISCAS’89 benchmarks. Categories and Subject Descriptors J.6 [Computer-Aided Engineering]: Computer-aided design |
| File Format | |
| Publisher Date | 2005-01-01 |
| Access Restriction | Open |
| Subject Keyword | Care State Boolean Satisfiability Robust Sat Solver Sequential Equivalence Bounded Sequential Problem Sequential Problem Effective Method Bounded Model Checking Sat-based Bounded Sequential Problem Sat Solver Search Space Subject Descriptor Computer-aided Design Original Problem Popular Engine Computer-aided Engineering Design Care State Verification World |
| Content Type | Text |