Loading...
Please wait, while we are loading the content...
Similar Documents
Power-optimal Repeater Insertion Considering Vdd and Vth as Design Freedoms ∗
| Content Provider | CiteSeerX |
|---|---|
| Abstract | This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion lengths, repeater sizes, and Vdd and Vth levels for a net with a delay target, and it reduces more than 50 % power over a previous work which does not consider Vdd and Vth optimization. This work further presents the power saving when multiple Vdd and Vth levels are used in repeater insertion at the full-chip level. Compared to the case with single Vdd and Vth suggested by ITRS, optimized dual Vdd and dual Vth reduce overall global interconnect power by 47%, 28% and 13 % for 130nm, 90nm and 65nm technology nodes, respectively, but extra Vdd or Vth levels only give marginal improvement. We also show that an optimized single Vth reduce interconnect power almost as effective as dual-Vth does, in contrast to the need of dual Vth for logic circuits. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Vth Level Power-optimal Repeater Insertion Considering Vdd Design Freedom Dual Vth Dual Vdd Vth Optimization Technology Node Multiple Vdd Repeater Size Repeater Insertion Optimal Repeater Insertion Length Delay Constraint Delay Target Analytical Repeater Insertion Method Extra Vdd Single Net Logic Circuit Full-chip Level Single Vdd Marginal Improvement Overall Global Interconnect Power Interconnect Power Optimized Single Vth |
| Content Type | Text |
