Loading...
Please wait, while we are loading the content...
Similar Documents
Instruction Queue Based Transient Error Identification and Correction through Cost-Effective Hardware ECC ABSTRACT
| Content Provider | CiteSeerX |
|---|---|
| Author | Stojanovic, Vladimir Bahar, R. Iris Dworak, Jennifer Weiss, Richard |
| Abstract | Major sources of transient errors in microprocessors today include noise and single event upsets. As feature sizes and voltages are reduced to create faster, more efficient, and more computationally powerful processors, these errors will increase significantly. We show that (contrary to conventional wisdom) error correction codes (ECC) can be efficiently utilized to manage these errors as instructions are being processed through the microprocessor pipeline. We analyze some of the tradeoffs involved in a hardware implementation of ECC for the instruction queue with respect to performance, power, area, and reliability. While this paper focuses specifically on the instruction queue, our approach can be generalized to other data structures within the microprocessor, such as the register file and reorder buffer. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Instruction Queue Transient Error Identification Cost-effective Hardware Ecc Abstract Reorder Buffer Microprocessor Pipeline Single Event Upset Register File Microprocessor Today Feature Size Error Correction Code Major Source Conventional Wisdom Hardware Implementation Transient Error Powerful Processor |
| Content Type | Text |
| Resource Type | Article |
