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A Hybrid Radix-4/Radix-8 LOWPower, High Speed Multiplier Architecture for Wide Bit Widths
| Content Provider | CiteSeerX |
|---|---|
| Author | Cherkauerl, Brian S. Friedrnan, E. G. |
| Abstract | Abstract – A hybrid radix-4/radix-8 architecture targeted for high bit multipliers is presented as a compromise between the high speed of a radix-4 multiplier architecture and the low power dissipation of a radix-8 multiplier architecture. In this hybrid radix-4/radix-8 multiplier architecture, the performance bottleneck of a radix-8 multiplier, the generation of three times the multiplicand for use in generating the radix-8 partial product, is performed in parallel with the reduction of the radix+ partird products rather than serially, as in a radix-8 multiplier. This hybrid radix+radix-8 multiplier architecture requires 13 % less power for a 64 x 64 bit multiplier, and results in only a 9 % increase in delay, as com-“pared with a radix ~ implementation, When supply voltage is sealed such that all multipliers exhibit the same delay, the 64 x 64 bit hybrid radixJVradix-8 multiplier dissipates less power than either the radix-4 or radix-8 multipliers. The hybrid radix-4/radix-8 amhiteeture is therefore appropriate for those applications that must dissipate minimal power and operate at high speeds. I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Wide Bit Width Radix-8 Multiplier Hybrid Radix-4 Radix-8 Lowpower High Speed Multiplier Architecture High Speed Hybrid Radix-4 Radix-8 Amhiteeture Hybrid Radix-4 Radix-8 Architecture Bit Hybrid Radixjvradix-8 Multiplier Low Power Dissipation Radix Partird Product Radix Implementation Radix-8 Partial Product Hybrid Radix Radix-8 Multiplier Architecture High Bit Multiplier Radix-8 Multiplier Architecture Hybrid Radix-4 Radix-8 Multiplier Architecture Minimal Power Radix-4 Multiplier Architecture Performance Bottleneck Supply Voltage |
| Content Type | Text |
