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Quantifying and reducing the effects of wrong-path memory references in cache-coherent multiprocessor systems (2006)
| Content Provider | CiteSeerX |
|---|---|
| Author | Sendag, Resit Yilmazer, Ayse Yi, Joshua J. Uht, Augustus K. |
| Description | International Parallel and Distributed Processing Symposium |
| Abstract | High-performance multiprocessor systems built around out-of-order processors with aggressive branch predictors execute many memory references that turn out to be on a mispredicted branch path. Previous work that focused on uniprocessors showed that these wrong-path memory references may pollute the caches by bringing in data that are not needed on the correct execution path and by evicting useful data or instructions. Additionally, they may also increase the amount of cache and memory traffic. On the positive side, however, they may have a prefetching effect for memory references on the correct path. While computer architects have thoroughly studied the impact of wrong-path effects in uniprocessor systems, there is no previous work on its effects in multiprocessor systems. In this paper, we explore the effects of wrongpath memory references on the memory system behavior of shared-memory multiprocessor (SMP) systems for both broadcast and directory-based cache coherence. Our results show that these wrong-path memory references can increase the amount of cache-to-cache transfers by 32%, invalidations by 8 % and 20 % for broadcast and directorybased SMPs, respectively, and the number of writebacks by up to 67 % for both systems. In addition to the extra coherence traffic, wrong-path memory references also increase the number of cache line state transitions by 21% and 32 % for broadcast and directory-based SMPs, respectively. In order to reduce the performance impact of these wrong-path memory references, we introduce two simple mechanisms – filtering wrong-path blocks that are not likely-to-be-used and wrong-path aware cache replacement – that yield speedups of up to 37%. 1 |
| File Format | |
| Publisher Date | 2006-01-01 |
| Access Restriction | Open |
| Subject Keyword | Out-of-order Processor Performance Impact Memory System Behavior Aggressive Branch Predictor Wrong-path Block Correct Path Positive Side Extra Coherence Traffic Wrong-path Effect Cache Line State Transition Cache-coherent Multiprocessor System Computer Architect Memory Traffic Branch Path Correct Execution Path Wrongpath Memory Reference Cache-to-cache Transfer Wrong-path Aware Cache Replacement Prefetching Effect Directory-based Cache Coherence Wrong-path Memory Reference Shared-memory Multiprocessor Memory Reference High-performance Multiprocessor System Many Memory Reference Simple Mechanism Useful Data Uniprocessor System Directory-based Smps Multiprocessor System |
| Content Type | Text |
| Resource Type | Conference Proceedings Article |
