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Power Issues Related to Branch Prediction
| Content Provider | CiteSeerX |
|---|---|
| Author | Dharmesh Parikh, Y. Kevinskadron, Y. Yan Zhang, Z. Marco Barcella, Z. Mircea R. Stan, Z. |
| Abstract | This paper explores the role of branch predictor organization in power/energy/performance tradeoffs for processor design. We find that as a general rule, to reduce overall energy consumption in the processor it is worthwhile to spend more power in the branch predictor if this results in more accurate predictions that improve running time. Two techniques, however, provide substantial reductions in power dissipation without harming accuracy. Banking reduces the portion of the branch predictor that is active at any one time. And a new on-chip structure, the prediction probe detector (PPD), can use pre-decode bits to entirely eliminate unnecessary predictor and branch target buffer (BTB) accesses. Despite the extra power that must be spent accessing the PPD, it reduces local predictor power and energy dissipation by about 45 % and overall processor power and energy dissipation by 5–6%. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Branch Prediction Power Issue Related Branch Predictor Energy Dissipation Pre-decode Bit New On-chip Structure Local Predictor Power Accurate Prediction Unnecessary Predictor Overall Energy Consumption Branch Target Buffer Prediction Probe Detector Power Energy Performance Tradeoff Power Dissipation General Rule Substantial Reduction Overall Processor Power Extra Power Branch Predictor Organization Processor Design |
| Content Type | Text |
| Resource Type | Article |
