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Thermal via placement in 3D ICs (2005)
| Content Provider | CiteSeerX |
|---|---|
| Author | Goplen, Brent |
| Description | As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promising way of mitigating thermal issues by lowering the thermal resistance of the chip itself. However, thermal vias take up valuable routing space, and therefore, algorithms are needed to minimize their usage while placing them in areas where they would make the greatest impact. With the developing technology of three-dimensional integrated circuits (3D ICs), thermal problems are expected to be more prominent, and thermal vias can have a larger impact on them than in traditional 2D ICs. In this paper, thermal vias are assigned to specific areas of a 3D IC and used to adjust their effective thermal conductivities. The thermal via placement method makes iterative adjustments to these thermal conductivities in order to achieve a desired maximum temperature objective. Finite element analysis (FEA) is used in formulating the method and in calculating temperatures quickly during each iteration. As a result, the method efficiently achieves its thermal objective while minimizing the thermal via utilization. |
| File Format | |
| Language | English |
| Publisher Date | 2005-01-01 |
| Publisher Institution | in Proceedings of the International Symposium on Physical Design |
| Access Restriction | Open |
| Subject Keyword | New Physical Design Paradigm Effective Thermal Conductivity Specific Area Thermal Resistance Three-dimensional Integrated Circuit Thermal Conductivity Thermal Objective Placement Method Iterative Adjustment Thermal Issue Promising Way Thermal Problem Thermal Vias Integrated Circuit Finite Element Analysis Desired Maximum Temperature Objective |
| Content Type | Text |
| Resource Type | Article |
