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A 3.125Gb/s Clock and Data Recovery Circuit Using 1/4-Rate Technique
| Content Provider | CiteSeerX |
|---|---|
| Abstract | Abstract—This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in range without using the reference clock. The proposed CDR was implemented using a 1/4-rate bang-bang type phase detector (PD) and a ring voltage controlled oscillator (VCO). The CDR circuit has been fabricated in a standard 0.18 CMOS technology. It occupies an active area of 1 x 1 and consumes 90 mW from a single 1.8V supply. Keywords—Clock and Data Recovery (CDR), 1/4-rate frequency detector (QRFD), 1/4-rate phase detector. I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | 4-rate Technique High Speed Application Vco Frequency Reference Clock Data Recovery Circuit Proposed Frequency Detector 4-rate Bang-bang Type Phase Detector Data Recovery Ring Voltage Cmos Technology Cdr Circuit Active Area Low Jitter Operation New Clock Keywords Clock 4-rate Frequency Detector Pull-in Range 4-rate Phase Detector |
| Content Type | Text |
