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ARRAY SYNTHESIS IN SYSTEMC HARDWARE COMPILATION
| Content Provider | CiteSeerX |
|---|---|
| Author | Ditmar, Johan |
| Abstract | This paper discusses the mapping of arrays in a highlevel SystemC description to hardware. Normally, arrays are implemented as register files using general purpose logic. Modern FPGAs however contain a large number of RAM blocks which can used to implement arrays instead. Memories have a limited number of ports and mapping arrays to multiport memories involves assigning each array access to a port. Whilst in RTL synthesis this choice is made by the designer, hardware compilation does not offer this level of control. In this paper, an algorithm is presented that automatically assigns accesses to ports such that no memory port is ever accessed more than once in a clock cycle. Unlike previous methods, the proposed algorithm assigns accesses to read/write-only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories. The method has been implemented in a commercial SystemC hardware compiler and results show a significant reduction in logic when implementing arrays in memory. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Array Synthesis Systemc Hardware Compilation Previous Method Clock Cycle Array Access Rtl Synthesis Limited Number Highlevel Systemc Description Register File General Purpose Logic Memory Port Modern Fpgas Mapping Array Read-write Port Ram Block Assignment Problem Hardware Compilation Commercial Systemc Hardware Compiler Assigns Access Significant Reduction Write-only Port Wider Range |
| Content Type | Text |
| Resource Type | Article |
