Loading...
Please wait, while we are loading the content...
Similar Documents
Efficient Exploration of Bus-Based System-on-Chip Architectures
| Content Provider | CiteSeerX |
|---|---|
| Abstract | Abstract—Separation between computation and communication in system design allows system designers to explore the communication architecture independently after component selection and mapping decision is made. In this paper, we present an iterative two-step exploration methodology for bus-based on-chip communication architecture for multitask applications. We assume that the memory traces from the processing components are given. The proposed methodology uses a static performance estimation technique extended for multitask applications to reduce the design space quickly and drastically and applies a trace-driven simulation to the reduced set of design candidates for accurate performance estimation. For the case that local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. Experimental results show that the proposed methodology achieves significant performance gain by optimizing on-chip communication only, up to almost 100 % compared with an initial single shared bus architecture, in both two real-life examples, a four-Channel digital video recorder and an equalizer for OFDM DVB-T receiver. Index Terms—Communication architecture, design space exploration, memory allocation, multitask, performance estimation. I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Efficient Exploration Bus-based System-on-chip Architecture Design Space Memory Allocation Multitask Application Bus Contention On-chip Communication Four-channel Digital Video Recorder Significant Performance Gain System Design Bus Architecture Component Selection System Designer Communication Architecture Proposed Methodology Local Memory Traffic Index Term Communication Architecture Important Axis Ofdm Dvb-t Receiver Mapping Decision Design Candidate Trace-driven Simulation Design Space Exploration Memory Traffic Bus-based On-chip Communication Architecture Accurate Performance Estimation Iterative Two-step Exploration Methodology Real-life Example Memory Trace Processing Component Abstract Separation Static Performance Estimation Technique Experimental Result Performance Estimation |
| Content Type | Text |
