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Clustering Based Pruning for Statistical Criticality Computation under Process Variations
| Content Provider | CiteSeerX |
|---|---|
| Author | Mogal, Hushrav D. Qian, Haifeng Sapatnekar, Sachin S. Bazargan, Kia |
| Abstract | Abstract — We present a new linear time technique to compute criticality information in a timing graph by dividing it into “zones”. Errors in using tightness probabilities for criticality computation are dealt with using a new clustering based pruning algorithm which greatly reduces the size of circuitlevel cutsets. Our clustering algorithm gives a 150X speedup compared to a pairwise pruning strategy in addition to ordering edges in a cutset to reduce errors due to Clark’s MAX formulation. The clustering based pruning strategy coupled with a localized sampling technique reduces errors to within 5 % of Monte Carlo simulations with large speedups in runtime. I. INTRODUCTION AND PREVIOUS WORK With scaling of technology, process parameter variations render the circuit delay as unpredictable [6], making sign-off ineffective in assuring against chip failure. Recent works concerning Statistical Static Timing Analysis (SSTA) in [1], [9] deal with this issue by treating the delay of gates and |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Statistical Criticality Computation Process Variation Chip Failure Criticality Information Localized Sampling Technique Process Parameter Variation New Clustering Monte Carlo Simulation Tightness Probability Circuitlevel Cutsets New Linear Time Technique Criticality Computation Introduction Previous Work Circuit Delay Large Speedup Clark Max Formulation Timing Graph Statistical Static Timing Analysis |
| Content Type | Text |
