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Block Alignment in 3D Floorplan Using Layered TCG (2006)
| Content Provider | CiteSeerX |
|---|---|
| Author | Law, Jill H. Y. |
| Abstract | In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as technology advances into the deep submicron era. 3D chip is a feasible solution to these problems. It has been shown that interconnect lengths can be greatly reduced in 3D ICs. In this paper, a novel 3D floorplan representation namely Layered Transitive Closure Graph (LTCG) is proposed, which is based on the Transitive Closure Graph (TCG) representation for 2D non-slicing floorplans. In LTCG, we can impose topological relationships between both blocks of the same layer and blocks of different layers. Experimental results have shown that LTCG is very promising for multi-layer floorplanning and can handle the inter-layer alignment problem effectively. |
| File Format | |
| Publisher Date | 2006-01-01 |
| Access Restriction | Open |
| Subject Keyword | Floorplan Using Layered Tcg Abstract Block Alignment Layered Transitive Closure Graph Circuit Complexity Floorplan Representation Topological Relationship Interconnect Delay Subject Descriptor Feasible Solution Interconnect Length Gate Delay Long On-chip Wire Modern Ic Design Computer Application Inter-layer Alignment Problem Technology Advance Transitive Closure Graph Computer-aided Design Non-slicing Floorplans Design Aid Placement Different Layer Deep Submicron Era Multi-layer Floorplanning Experimental Result |
| Content Type | Text |
