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High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with Multiple Supplies
| Content Provider | CiteSeerX |
|---|---|
| Author | Man, Hugo De Gielen, Georges Engels, Marc Bolsens, Ivo |
| Abstract | Substrate noise generated by large digital circuits degrades the performance of analog circuits sharing the same substrate. Existing approaches usually extract the model of the substrate from the layout information and then simulate the extracted transistor-level netlist with this substrate model using a transistor-level simulator. For large digital circuits, the substrate simulation is however not feasible with a transistor-level simulator. In our previous work, it has been demonstrated that efficient and accurate simulation of substrate noise generation at gatelevel is feasible. In this paper several important extensions to our previous work are introduced: modeling of IO cells, modeling of input transition time and load dependency and the extraction methodology of an equivalent substrate model within multiple supply domains. Experimental results show an improved accuracy (6.3 % error on RMS substrate voltage with respect to a full SPICE level simulation) with these extensions, while maintaining a large speedup with respect to SPICE simulations. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Large Digital Circuit Substrate Noise Generation High-level Simulation Multiple Supply Transistor-level Simulator Equivalent Substrate Model Substrate Simulation Load Dependency Substrate Model Improved Accuracy Accurate Simulation Full Spice Level Simulation Layout Information Io Cell Substrate Noise Extraction Methodology Large Speedup Multiple Supply Domain Input Transition Time Paper Several Important Extension Spice Simulation Rms Substrate Voltage Experimental Result Extracted Transistor-level Netlist Analog Circuit |
| Content Type | Text |
| Resource Type | Article |
