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A real time SAR processor implementation with FPGA
| Content Provider | CiteSeerX |
|---|---|
| Author | Lesnik, C. Kawalec, A. Serafin, P. |
| Abstract | Great numerical complexity is a characteristic of synthetic aperture radar (SAR) image synthesis algorithms that poses a particularly serious problem for real-time application. Advances in the operating speed and density of the field programmable gate arrays (FPGA) have allowed many high-end signal processing applications to be solved in commercially available hardware. A real-time SAR image processor was designed and implemented with the commercial off the shelf (COTS) hardware. The hardware was based on the Xilinx Virtex 5 FPGA devices. Under the assumption of squinted SAR geometry and range migration effect present the SAR image synthesis algorithm was developed and implemented. The results of the processor tests conducted with simulated and real raw SAR signals are presented in the paper. |
| File Format | |
| Access Restriction | Open |
| Content Type | Text |
