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A 0.8V, 560fJ/bit, 14Gb/s Injection-Locked Receiver with Input Duty-Cycle Distortion Tolerable Edge-Rotating 5/4X Sub-Rate CDR in 65nm CMOS
| Content Provider | CiteSeerX |
|---|---|
| Author | Li, Hao Chen, Shuai Yang, Liqiong Bai, Rui Hu, Weiwu Zhong, Freeman Y. Palermo, Samuel Chiang, Patrick Yin |
| Abstract | A quarter-rate forwarded-clock receiver utilizes an edge-rotating 5/4X sub-rate CDR for improved jitter tolerance with low power overhead relative to conventional 2X oversampling CDR systems. Low-voltage operation is achieved with efficient quarter-rate clock generation from an injection-locked oscillator (ILO) and through automatic independent phase rotator control that optimizes timing margin of each input quantizer in the presence of receive-side clock static phase errors and transmitter duty-cycle distortion (DCD). Fabricated in GP 65nm CMOS, the receiver operates up to 16Gb/s with a BER<10-12, achieves a 1MHz phase tracking bandwidth, tolerates ±50%UIpp DCD on input data, and has 14Gb/s energy efficiency of 560fJ/bit at VDD=0.8V. |
| File Format | |
| Access Restriction | Open |
| Content Type | Text |
