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Test Pattern Generator (2001)
| Content Provider | CiteSeerX |
|---|---|
| Author | Guiller, L. Landrault, C. Pravossoudovitch, S. Wunderlich, H. J. |
| Abstract | Abstract: In this paper, we present a new low power BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique. The fault coverage and the test time are roughly the same as those achieved using a standard BIST scheme. The area overhead is nearly negligible and there is no penalty on the circuit delay. The proposed BIST scheme does not require any circuit design modification beyond the parallel BIST technique, is easily implemented and has low impact on the design time. It has been implemented based on an LFSR-based TPG, but can also be designed using a cellular automata. Reductions of the energy, average power and peak power consumption during test operation are up to 94%, 55 % and 48 % respectively for ISCAS and MCNC benchmark |
| File Format | |
| Publisher Date | 2001-01-01 |
| Access Restriction | Open |
| Subject Keyword | Test Pattern Generator Test Operation Clock Tree Numerous Advantage Test Time Design Time Lfsr-based Tpg Average Power Parallel Bist Technique Peak Power Consumption Modified Clock Scheme Test Vector Bist Scheme Low Impact Area Overhead Switching Activity Fault Coverage Cellular Automaton Circuit Delay Standard Bist Scheme Mcnc Benchmark Circuit Design Modification Low Power Energy Bist Technique |
| Content Type | Text |
| Resource Type | Article |
