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Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics (2004)
| Content Provider | CiteSeerX |
|---|---|
| Author | Cong, Jason Lin, Yan He, Lei Li, Fei |
| Abstract | Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use pre-defined dual-Vdd and dual-Vt fabrics to reduce FPGA power. We design FPGA circuits with dual-Vdd/dual-Vt to e#ectively reduce both dynamic power and leakage power, and define dual-Vdd/dual-Vt FPGA fabrics based on the profiling of benchmark circuits. We further develop CAD algorithms including power-sensitivity based voltage assignment and simulated-annealing based placement to leverage such fabrics. Compared to the conventional fabric using uniform Vdd/Vt at the same target clock frequency, our new fabric using dual Vt achieves 9% to 20% power reduction. However, the pre-defined FPGA fabric using both dual Vdd and dual Vt only achieves on average 2% extra power reduction. It is because that the pre-designed dual-Vdd layout pattern introduces non-negligible performance penalty. Therefore, programmability of supply voltage is needed to achieve significant power saving for dual-Vdd FPGAs. To our best knowledge, it is the first in-depth study on applying both dual-Vdd and dual-Vt to FPGA considering circuits, fabrics and CAD algorithms. |
| File Format | |
| Publisher Date | 2004-01-01 |
| Access Restriction | Open |
| Subject Keyword | Uniform Vdd Vt Dual Vdd Benchmark Circuit Dual-vt Fabric Voltage Assignment Pre-defined Fpga Fabric Fpga Circuit Dual-vdd Fpgas First In-depth Study Extra Power Reduction Cad Algorithm Dual-vdd Dual-vt Fpga Fabric Significant Power Dual Vt Dual-vdd Dual-vt Fpga Power Target Clock Frequency Conventional Fabric Uniform Threshold Voltage Vt Dynamic Power |
| Content Type | Text |
