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Architecture and Hardware Support for Real-time Scheduling of Packet Streams
| Content Provider | CiteSeerX |
|---|---|
| Author | Krishnamurthy, Raj Yalamanchili, Sudhakar West, Richard Schwan, Karsten |
| Abstract | 1) Scheduling of packet streams in real-time (as opposed to virtual-time) is necessary to make classes of scheduling guarantees and maximize link utilization. 2) Scheduling at wire-speeds for optical multi-gigabit links and the emerging 10GEA (10 Gigabit Ethernet Alliance) standard necessitates scheduling decisions be guaranteed to be completed in a packet time. 3) Architecture and implementations that can meet cost/performance requirements across a range of environments without ASIC re-engineering overheads. 4) It is necessary to trade-off scheduler throughput in packets/sec with quality of service and scheduling granularity, e.g., scheduling at the packet level vs. MPEG frame level. Proposed Solution We propose to address these problems through the use of a powerful scheduling discipline and a flexible target architecture that combines a commercial microprocessor datapath with a tightly coupled reconfigurable logic component such as a FPGA. Such system on a chip architectures have been announced in the recent past and provide potential hardware solutions for applications that demand both flexibility and the performance that can be achieved via hardware customization. Our approach implements the compute intensive scheduling decision logic within the configurable logic component while control and data movement is handled by the microprocessor [2]. The scheduling discipline for which we propose hardware solutions is Dynamic |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Cost Performance Requirement Trade-off Scheduler Throughput Decision Logic Packet Level V Flexible Target Architecture Hardware Customization Potential Hardware Solution Gigabit Ethernet Alliance Commercial Microprocessor Datapath Asic Re-engineering Overhead Chip Architecture Mpeg Frame Level Hardware Solution Packet Stream Scheduling Discipline Optical Multi-gigabit Link Packet Time Reconfigurable Logic Component Configurable Logic Component Powerful Scheduling Discipline Link Utilization |
| Content Type | Text |
