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An Efficient SQRT Architecture of Carry Select Adder Design by HA and Common Boolean Logic
| Content Provider | CiteSeerX |
|---|---|
| Author | Kalpana, Ragutla |
| Abstract | ABSTRACT: As we are aware that carry select adder is the fastest one amongdata processing element, on the other hand due to having pairs of ripple carry adder structure traditional carry select adder consumes more area. So proposed scheme is to developa low power and low area half adder based (CSLA) using simple using common Boolean logic (CBL), where it employs one half adders to perform the summation operation for the common Boolean logic (CBL) and carry zero respectively. Half adder and CBL have to be designed where half adder requires one XOR gate, one AND gate where CBL requires only one NOT as well as one OR gate. Here also architecures like 8-bit, 16-bit, 32-bit, 64-bit square root carry select adder (SQRT CSLA) is compared with regular one and modified also. The results show there is a great reduction in area and power consumption. Our work shows the better performance in case of minimized delay, less area and low power.The obtained results from the simulation clearly proves our proposed CSLA scheme is dominates the regular SQRT CSLA. Keywords:ASIC, Power, area and delay efficient, BEC, SQRT CSLA. I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Common Boolean Logic Carry Select Adder Design Half Adder Efficient Sqrt Architecture Low Power Sqrt Csla Xor Gate Low Area Half Adder 64-bit Square Root Proposed Scheme Amongdata Processing Element Delay Efficient Summation Operation Minimized Delay Great Reduction Regular Sqrt Csla Power Consumption Obtained Result Csla Scheme |
| Content Type | Text |
| Resource Type | Article |
