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IMPLEMENTATION OF MULTI-SLAVE INTERFACE FOR AXI BUS Anitha.H.T
| Content Provider | CiteSeerX |
|---|---|
| Author | Manasa B., T. |
| Abstract | With the need of application, chip with a single processor can’t meet the need of more and more complex computational task. We are able to integrate multiple processors on a chip. Multi-Processor System on Chip (MPSoC) which gives a solution to this requires efficient on-chip communication architectures to support high data bandwidth and increase parallelism. The traditional form of interconnection between multiple cores usually is on-chip bus (such as AHB and Avalon), which determiners the performance of MPSoC. However, traditional buses only allow one master to access one slave at one time, which badly restricts the performance of the whole system. In this paper we focus on the design and implementation of a multi slave interface for AXI bus, which translates data in burst, maximal length of which is up to 16 transactions. Besides, it only needs to translate the head address of the burst in this transaction. Owing to that feature, multiple masters accessing multiple slaves at one time becomes possible in sharing address bus architecture. Besides, there are five independent data transfer channels, making it translate data in high speed and efficiently. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Multi-slave Interface Axi Bus Anitha High Data Bandwidth Maximal Length Multiple Master On-chip Bus Independent Data Transfer Channel Complex Computational Task Axi Bus Translate Data Multiple Slave Whole System Multi-processor System Multi Slave Interface Efficient On-chip Communication Architecture Traditional Form High Speed Single Processor Multiple Core Head Address Multiple Processor Traditional Bus Address Bus Architecture |
| Content Type | Text |
| Resource Type | Article |
