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A Novel Area-Efficient Binary Adder
| Content Provider | CiteSeerX |
|---|---|
| Author | Furber, S. B. Liu, J. |
| Abstract | A novel circuit for binary addition based on a parallel-prefix carry structure is presented. This circuit uses a recoding of the conventional carry kill and generate terms to yield a number of improvements over previous designs. In particular, a single circuit produces both the carry sig-nals and the Sum, Sum + 1 data that is required for a carry selection circuit, supporting a range of possible implemen-tations all of which have high performance, regular layout and good area-efficiency. The simple design also leads to good power-efficiency. Binary adders based on this technique have been used in the ARM9TDMI, the ARM Piccolo DSP coprocessor, and the AMULET3 asynchronous ARM processor. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Novel Area-efficient Binary Adder Binary Addition Carry Selection Circuit Regular Layout Carry Sig-nals Previous Design Arm Piccolo Dsp Coprocessor Possible Implemen-tations Generate Term Parallel-prefix Carry Structure Single Circuit Novel Circuit Amulet3 Asynchronous Arm Processor Good Power-efficiency Binary Adder Good Area-efficiency High Performance Conventional Carry Kill Simple Design |
| Content Type | Text |
