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Enhance Memory-Level Parallelism via Recovery-Free Value Prediction (2003)
| Content Provider | CiteSeerX |
|---|---|
| Author | Zhou, Huiyang Conte, Thomas M. |
| File Format | |
| Language | English |
| Publisher Date | 2003-01-01 |
| Publisher Institution | Proc. 2003 Int’l Conf. Supercomputing (ICS-03 |
| Access Restriction | Open |
| Subject Keyword | Complex Prediction Validation Misprediction Recovery Mechanism Minor Hardware Modification Simple Stride Value Predictor Enhance Memory-level Parallelism Execution Time Slow Memory Operation Memory-level Parallelism Value Prediction Novel Technique Instruction-level Parallelism Memory-intensive Workload Cache Miss Sequential Cache Miss Multiple Cache Miss Value-speculative Execution Arithmetic Computation Enable Aggressive Memory Disambiguation Significant Speedup True Data Dependency Experimental Result Recovery-free Value Prediction Ever-increasing Computational Power Contemporary Microprocessor |
| Content Type | Text |
| Resource Type | Article |