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Implementation of on Chip Data Bus Using Pre Emphasis Signaling
| Content Provider | CiteSeerX |
|---|---|
| Author | Dedge, Pallavi Pune, Scoe Badwaik, S. C. |
| Abstract | This work describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25- μ m complementary metal– oxide–semi- conductor (CMOS) technology attains an aggregate signaling data rate of 64 Gb/s over 5–10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5–48.7-mW power dissipation. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Complementary Metal Bus Power Dissipation Differential Current-mode Bus Architecture 16-b Bus Core High-data Rate Driver Pre-emphasis Aggregate Signaling Data Rate 10-mm-long Lossy Interconnects Semi Conductor Signal Delay Latency On-chip Global Interconnects 7-mw Power Dissipation |
| Content Type | Text |
