Loading...
Please wait, while we are loading the content...
Similar Documents
A Unified Approach for the Synthesis of Self-Testable Finite State (1993)
| Content Provider | CiteSeerX |
|---|---|
| Author | Eschermann, Bernhard Wunderlich, Hans-Joachim |
| File Format | |
| Language | English |
| Publisher Date | 1993-01-01 |
| Publisher Institution | Machines,” 28th ACM/IEEE Des. Autom. Conf |
| Access Restriction | Open |
| Subject Keyword | Unified Approach Benchmark Circuit Self-test Hardware Hardware Overhead Parallel Self-testable Circuit Self-testable Circuit Abstract Conventionally Self-test Hardware Pattern Generator Novel Target Structure Self-testable Finite State Signature Register Design Method Sequential Circuit |
| Content Type | Text |
| Resource Type | Article |