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Time-to-Digital Converter with 3-ps Resolution and Digital Linearization Algorithm
| Content Provider | CiteSeerX |
|---|---|
| Author | Zanuso, Marco Levantino, Salvatore Puggelli, Alberto Samori, Carlo Lacaita, Andrea L. |
| Abstract | Abstract—This paper presents a digital scrambling technique to improve the linearity of flash time-to-digital converters (TDCs) with sub-gate-delay time resolution. Thanks to this approach, a flash TDC using N time arbiters behaves as a quasi-stochastic TDC with an equivalent number of samples equal to N2, at the negligible area cost of doubling the number of minimum load capacitors. The concept is proved in a 65-nm CMOS technology 40MHz TDC, which achieves a 3ps resolution. The differential nonlinearity is reduced from 1LSB to less than 0.2LSB. I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | 3-ps Resolution Digital Linearization Algorithm Time-to-digital Converter Minimum Load Capacitor Flash Tdc Negligible Area Cost Differential Nonlinearity Sub-gate-delay Time Resolution Quasi-stochastic Tdc Flash Time-to-digital Converter Digital Scrambling Technique Time Arbiter Behaves Equivalent Number 65-nm Cmos Technology |
| Content Type | Text |
