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A sub-mW MPEG-4 motion estimation processor core for mobile video application (2004)
| Content Provider | CiteSeerX |
|---|---|
| Author | Kuroda, Y. Miyakoshi, J. Miyama, M. Imamura, K. Hashimoto, H. Yoshimoto, M. |
| Abstract | This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a Gradient Descent Search algorithm whose computation power is only 7 % of the conventional 1:4-subsampling search, producing higher picture quality. Another feature is an optimized SIMD datapath architecture to decrease a clock frequency and an operating voltage. It has been fabricated with CMOS 5-metal 0.18 um technology. The measured power consumption to process a QCIF 15 fps video is 0.4 mW under 0.85 MHz@1.0 V. |
| File Format | |
| Journal | IEEE Journal of Solid-State Circuits |
| Language | English |
| Publisher Date | 2004-01-01 |
| Access Restriction | Open |
| Subject Keyword | Mobile Video Application Optimized Simd Datapath Architecture Sub-mw Motion Estimation Processor Core Gradient Descent Search Algorithm Um Technology Mpeg-4 Video 4-subsampling Search Computation Power Cmos 5-metal Operating Voltage Clock Frequency Measured Power Consumption Picture Quality Fps Video |
| Content Type | Text |
| Resource Type | Article |
