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Delay testing of partially depleted silicon-on-insulator (pd-soi) circuits.
| Content Provider | CiteSeerX |
|---|---|
| Author | Macdonald, Eric Touba, Nur A. |
| Abstract | has garnered more attention recently with regards to replacing traditional bulk-silicon technology as the mainstream technology of choice for high-performance/low-power digital applications. The increase in performance is due to the buried oxide layer, which provides a dramatic decrease in the source and drain junction capacitance, as well as a reduction in the traditional back biasing resulting from the body effect. The reported performance increases have been between 20 % and 35%. However, this increase in performance comes at a cost of complexity from a performance measurement and delay testing perspective. Where the SOI transistor is faster than the bulk transistor, there exists a variation in delay caused by threshold voltage shifts that must be accounted for during manufacturing test. This paper explores these issues and proposes new test techniques for this promising technology. Index Terms—Delay testing, flip-flop design, silicon-on-insulator (SOI) testing. I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Delay Testing Partially Depleted Silicon-on-insulator Promising Technology New Test Technique Reported Performance Increase Flip-flop Design Bulk Transistor High-performance Low-power Digital Application Drain Junction Capacitance Threshold Voltage Shift Performance Measurement Index Term Delay Testing Dramatic Decrease Soi Transistor Mainstream Technology Body Effect Traditional Bulk-silicon Technology |
| Content Type | Text |
| Resource Type | Article |
