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CMOS Switched-Op-Amp-Based Sample-andHold Circuit (2000)
| Content Provider | CiteSeerX |
|---|---|
| Author | Dai, Liang Harjani, Ramesh |
| Abstract | Abstract—This paper presents a sample-and-hold design that is based on a switched-op-amp topology. Charge injection errors are greatly reduced by turning off transistors in the saturation region instead of the triode region as is the case for traditional MOS switches. The remaining clock feedthrough error is mostly signal-independent and is cancelled out by a pseudodifferential topology. Switched-op-amps are designed and fabricated in a 2-µ CMOS technology. The measurement results show that the harmonics are at least 78 dB below the signal level. Both the measurement results from fabricated IC’s and simulation results suggest the potential benefits of this approach in comparison to traditional switched-capacitor circuits. Index Terms—Analog–digital conversion, charge injection, sample-and-hold circuits, switched opamp. I. |
| File Format | |
| Journal | IEEE J. Solid-State Circuits |
| Language | English |
| Publisher Date | 2000-01-01 |
| Access Restriction | Open |
| Subject Keyword | Cmos Switched-op-amp-based Sample-andhold Circuit Measurement Result Sample-and-hold Design Potential Benefit Charge Injection Error Index Term Analog Digital Conversion Clock Feedthrough Error Sample-and-hold Circuit Pseudodifferential Topology Fabricated Ic Charge Injection Triode Region Traditional Switched-capacitor Circuit Traditional Mo Switch Cmos Technology Switched-op-amp Topology Simulation Result Saturation Region Signal Level |
| Content Type | Text |
| Resource Type | Article |
